1. Field of the Invention
The present invention relates to a structure of integrated surface field effect transistors particularly suited for the fabrication of ultra large scale integration (ULSI) devices.
2. Description of the Prior Art
The push to increase the density of integration of monolithically integrated semiconductor devices often forces the reduction of the size of single integrated devices without simultaneously being able to reduce supply voltages by a comparable scale factor. On the other hand also in ULSI devices certain characteristics of a surface field effect transistor cannot be traded off; namely:
(a) a sufficiently high gain under operating conditions; PA0 (b) a "punchthrough" voltage higher than the maximum operating voltage and consequently a certain reduction of the leakage current under cut-off conditions; PA0 (c) a positive shifting of possible "snap-back" phenomena beyond the so-called absolute maximum rating (AMR); PA0 (d) sturdiness and stability of electrical characteristics (i.e. threshold voltage and gain) even after an injection of hot carriers (electrons or holes) in the gate oxide (or equivalent dielectric); PA0 (e) preservation of a substantial integrity of the gate dielectric even after the injection of hot carriers or the occurence of electrostatic shocks (notably the effect of these phenomena is not normally evidenced by an immediate degradation of the electrical characteristics but eventually leads to a failure of the device after a certain period of operation). PA0 (1) presence of a strong electric field in the drain region which causes: the reaching of a "saturation" limit value of the mean velocity of carriers, impact ionization and a multiplication current in the drain junction; PA0 (2) presence of a sharp bend of the drain junction and reduction of the thickness of the gate dielectric in devices with a high level of integration which contribute to increase further the intensity of the electric field thus enhancing a so-called "gate-diode" behaviour; PA0 (3) proximity between intense electric field points in the silicon and the gate dielectric layer which favors the presence of hot carriers near the interface between the dielectric layer and the silicon; PA0 (4) a peculiar orientation of the electric field at the drain junction, which becomes more evident under certain operating conditions of the transistor, which favors the trapping of hot carriers in critical zones for the degradation of the electrical characteristics or in any case which can be presumably damaging for the integrity of the dielectric oxide (e.g. underneath the base of the lateral oxide spacers formed on the flanks of the gate electrode).
As it is well known to the skilled technician and amply described in literature, the (a) requisite imposes a precise trimming of certain fabrication steps while, for satisfying the (b) requisite, two alternative techniques are known: a first technique requires a deep ion implantation in the channel region, known as "antipunchthrough" implantation, of impurities of the same polarity of those already present in the same channel region (e.g. in the monocrystalline silicon substrate in which the transistor is made, i.e. a P-type region for an N-channel transistor and an N-type region for a P-channel transistor) for locally increasing the impurity concentration; an alternative technique which is normally used in relatively advanced fabrication processes and which is also known as the Double Diffused Drain (DDD) technique, consists in confining the depletion region of the source and drain junctions (diffused regions) by means of an ion implantation of impurities of polarity opposite to the polarity of the impurities used for forming the diffused regions, i.e. the drain and source junction regions themselves.
The requisites (c), (d) and (e) are all directly or indirectly connected to the physical phenomenon known as "multiplication" (of charge carriers) which is originated by the following physical factors:
In order for the integrated transistor to retain the above-mentioned requisites: (c), (d) and (e), different solutions are known such as: the drain extension technique (DE), the graduated drain doping technique (GDD) and the light drain doping technique (LDD). These techniques, through respectively different additional steps of the sequence of steps of the fabrication process, tend to "couple" the channel region of the transistor to the drain junction region (having a relatively high impurity concentration) through an intermediate region doped with impurities of the same type of the impurities of the drain region but having a concentration lower than the latter by at least one or two orders of magnitude. By comparison, the three known solutions cited above have well recognized relative advantages and drawbacks; however only the LDD technique may be practically implemented also in ULSI processes.